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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
SDA
SCL
C7
1
C6
2
C5
3
C4
4
C3
5
C2
6
C1
7
C0
8
ACK
9
Figure 15. Command Byte
SDA
SCL
D15
1
D14
2
D13
3
D12
4
D11
5
D10
6
D9
7
D8
8
ACK
9
D7
10
D6
11
D5
12
D4
13
D3
14
D2
15
D1
16
D0
17
NACK
OR ACK
18
Figure 16. Data Bytes
S
SDA
SCL
Figure 17. START and STOP Conditions
high-speed mode (HS mode), allowing bus speeds up
to 3.4MHz. Execute the following procedure to change
from FS mode to HS mode (see Figure 21).
1) Generate a START condition (S).
2) Send byte 00001XXX (X = don’t care). The MAX1385/
MAX1386 issue a NACK bit.
3) HS mode is entered on the 10th rising clock edge.
To remain in HS mode, use repeated START conditions
(Sr) in place of the normal STOP conditions (P) (see
Figure 22). All the same write and read formats sup-
ported in FS mode are supported in HS mode (with the
replacement of repeated START conditions for STOP
conditions). Generating a STOP condition (P) while in
HS mode changes the bus speed back to FS mode.
Sr
P
SPI Digital Serial Interface
The MAX1385/MAX1386 feature a 4-wire SPI-compati-
ble serial interface capable of supporting data rates up
to 16MHz. Full data transfers occur in 24-bit sections.
The first 8-bit byte is a command byte (C7–C0). The
next 16 bits are data bits (D15–D0). Clock signal SCL
may idle low or high but data is always clocked in on
the rising edge of SCL (CPOL = CPHA).
Write Format
Use the following sequence to write 16 bits of data to a
MAX1385/MAX1386 register (see Figure 18):
1) Pull CSB low to select the device.
2) Send the appropriate write command byte (see the
Command Byte section). The command byte is
clocked in on the rising edge of SCL.
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